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Intel, with partner Hewlett-Packard, developed a next generation 64-bit processor architecture called IA-64 (the 80x86 design was renamed IA-32) - the first implementation was named Itanium. Itanium core processor is not binary compatible with X86 processors, instead it has a separate compatibility unit in hardware to provide IA32 compatibility.

Itanium only allow memory operands in load and store operations. As Itanium was a 64-bit processor so could address memory up to 4 GByte of RAM. The processor uses Explicitly Parallel Instruction Computing (EPIC), in which the compiler lines up instructions for parallel execution. Features were added to ensure compatibility with both Intel x86 and HP UNIX applications.

During development, it was widely expected that this would become the dominant processor architecture for servers, workstations, and perhaps even desktops, bumping the ubiquitous x86 architecture, and providing an industry-standard architecture across an unprecedented range of computing platforms, but it didn’t happen so. The Itanium processor was specifically designed to provide a very high level of parallel processing, to enable high performance without requiring very high clock frequencies (which can lead to excessive power consumption and heat generation).


Key strengths of the Itanium architecture include, Up to 6 instructions/cycle: The Itanium processor can handle up to 6 simultaneous 64-bit instructions per clock cycle, and the dual-core version can support up to two software threads per core, Extensive xecution resources per core: 256 application registers (128 general purpose, 128 floating point) and 64 predicate registers, Large cache: 24MB in the dual-core version (12MB per core), providing data to each core at up to 48GB/s, Large address space: 50-bit physical / 64-bit virtual, Small, energy-efficient core: Since Itanium relies on the compiler for scheduling instructions for parallel throughput (other architectures rely on runtime optimization within the processor itself), it has fewer transistors in each core. This may be an advantage in current and future multi-core designs.


Itanium Microprocessor.

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The Pentium D is a series of microprocessors that was introduced by Intel at the spring 2005 Intel Developer Forum. A 9xx-series Pentium D package contains two Pentium 4 dies, unlike other multi-core processors (including the Pentium D 8xx-series) that place both cores on a single die. The Pentium D was the first announced multi-core CPU (along with its more expensive twin, the Pentium Extreme Edition) from any manufacturer intended for desktop computers. Intel underscored the significance of this introduction by predicting that by the end of 2006 over 70% of its shipping desktop CPUs would be multi-core.

Historically, processor manufacturers have responded to the demand for more processing power primarily by delivering faster processor speeds. However, the challenge of managing power and cooling requirements for today’s powerful processors has prompted a reevaluation of this approach to processor design. With heat rising incrementally faster than the rate at which signals move through the processor, known as clock speed, an increase in performance can create an even larger increase in heat. The answer is multi-core microprocessor.

For example, by moving from a single high-speed core, which generates a corresponding increase in heat, to multiple slower cores, which produce a corresponding reduction in heat, enterprises can potentially improve application performance while reducing their thermal output. A multi-core microprocessor is one which combines two or more independent processors into a single package, often a single integrated circuit (IC); to be more specific it has more than one execution unit with in a single integrated circuit.

A dual-core device contains only two independent microprocessor execution units, as shown in the figure below. In general, multi-core microprocessors allow a computing device to exhibit some form of thread-level parallelism (TLP) without including multiple microprocessors in separate physical packages. This form of TLP is often known as chip-level multiprocessing, or CMP. The Pentium D 820 runs in at 2.8GHz, is dual-core, its highlights are; it features two 16KB data caches in ddition to data cache, each core includes an Execution Trace Cache that stores up to 12 K decoded micro-ops in the order of program execution, Streaming SIMD Extensions 3(SSE3) significantly accelerates performance of digital media applications and includes additional integer and cache ability instructions that may improve other aspects of performance, Execute Disable Bit feature combined with a supported operating system, allows memory to be marked as executable and nonexecutable and if code attempts to run in non-executable memory the processor raises an error to the operating system, it also has internal performance counters for performance monitoring and event counting and it also includes a thermal monitor feature that allows motherboards to be more cost effective. Analysts have speculated that the clock rate race between Intel and AMD is largely over, with no more exponential gains in clock rate likely. Instead, as long as Moore's Law holds true, it is expected that the increasing number of transistors that chipmakers can incorporate into their CPUs will be used to increase CPU throughput through other methods, such as adding cores.


Pentium D Microprocessor

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The Itanium 2 is an IA-64 microprocessor developed jointly by Hewlett- Packard (HP) and Intel, and introduced on July 8, 2002. The first Itanium 2 processor (code-named McKinley) was substantially more powerful than the original Itanium processor, roughly doubling performance, and providing competitive performance across a range of data- and compute-intensive workloads. Several generations of Itanium 2 processors have followed. The Itanium 2 processor architecture is, dubbed Explicitly Parallel Instruction Computing (EPIC).

It is theoretically capable of performing roughly 8 times more work per clock cycle than other CISC and RISC architectures due to its Parallel Computing Micro-architecture. However, performance is heavily dependent on software compilers and their ability to generate code which efficiently uses the available execution units of the processor.

All Itanium 2 processors to date share a common cache hierarchy. They have 16 KB of Level 1 instruction cache and 16 KB of Level 1 data cache. The L2 cache is unified (both instruction and data) and is 256 KB. The Level 3 cache is also unified and varies in size from 1.5 MB to 24 MB. In an interesting design choice, the L2 cache contains sufficient logic to handle semaphore operations without disturbing the main ALU. The latest Itanium processor, however, features a split L2 cache, adding adedicated 1MB L2 cache for instructions and thereby effectively growing the original 256 KB L2 cache, which becomes a dedicated data cache. Most systems sold by enterprise server vendors that contain 4 or more processor sockets use proprietary Non-Uniform Memory Access (NUMA) architectures that supersede the more limited front side bus of 1 and 2 CPU socket servers.

The Itanium 2 bus is occasionally referred to as the Scalability Port, but much more frequently as the McKinley bus. It is a 200 MHz, 128-bit wide, double pumped bus capable of 6.4 GB/s — more than three times the bandwidth of the original Itanium bus, known as the Merced bus. In 2004, Intel released processors with a 266 MHz bus,
increasing bandwidth to 8.5 GB/s. In early 2005, processors with a 10.6 GB/s, 333 MHzbus were released.


Itanium 2 Microprocessor.