Itanium 2
Posted by Harisinh | Posted in | Posted on 4:33 AM
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The Itanium 2 is an IA-64 microprocessor developed jointly by Hewlett- Packard (HP) and Intel, and introduced on July 8, 2002. The first Itanium 2 processor (code-named McKinley) was substantially more powerful than the original Itanium processor, roughly doubling performance, and providing competitive performance across a range of data- and compute-intensive workloads. Several generations of Itanium 2 processors have followed. The Itanium 2 processor architecture is, dubbed Explicitly Parallel Instruction Computing (EPIC).
It is theoretically capable of performing roughly 8 times more work per clock cycle than other CISC and RISC architectures due to its Parallel Computing Micro-architecture. However, performance is heavily dependent on software compilers and their ability to generate code which efficiently uses the available execution units of the processor.
All Itanium 2 processors to date share a common cache hierarchy. They have 16 KB of Level 1 instruction cache and 16 KB of Level 1 data cache. The L2 cache is unified (both instruction and data) and is 256 KB. The Level 3 cache is also unified and varies in size from 1.5 MB to 24 MB. In an interesting design choice, the L2 cache contains sufficient logic to handle semaphore operations without disturbing the main ALU. The latest Itanium processor, however, features a split L2 cache, adding adedicated 1MB L2 cache for instructions and thereby effectively growing the original 256 KB L2 cache, which becomes a dedicated data cache. Most systems sold by enterprise server vendors that contain 4 or more processor sockets use proprietary Non-Uniform Memory Access (NUMA) architectures that supersede the more limited front side bus of 1 and 2 CPU socket servers.
The Itanium 2 bus is occasionally referred to as the Scalability Port, but much more frequently as the McKinley bus. It is a 200 MHz, 128-bit wide, double pumped bus capable of 6.4 GB/s — more than three times the bandwidth of the original Itanium bus, known as the Merced bus. In 2004, Intel released processors with a 266 MHz bus,
increasing bandwidth to 8.5 GB/s. In early 2005, processors with a 10.6 GB/s, 333 MHzbus were released.
Itanium 2 Microprocessor.
The Itanium 2 is an IA-64 microprocessor developed jointly by Hewlett- Packard (HP) and Intel, and introduced on July 8, 2002. The first Itanium 2 processor (code-named McKinley) was substantially more powerful than the original Itanium processor, roughly doubling performance, and providing competitive performance across a range of data- and compute-intensive workloads. Several generations of Itanium 2 processors have followed. The Itanium 2 processor architecture is, dubbed Explicitly Parallel Instruction Computing (EPIC).
It is theoretically capable of performing roughly 8 times more work per clock cycle than other CISC and RISC architectures due to its Parallel Computing Micro-architecture. However, performance is heavily dependent on software compilers and their ability to generate code which efficiently uses the available execution units of the processor.
All Itanium 2 processors to date share a common cache hierarchy. They have 16 KB of Level 1 instruction cache and 16 KB of Level 1 data cache. The L2 cache is unified (both instruction and data) and is 256 KB. The Level 3 cache is also unified and varies in size from 1.5 MB to 24 MB. In an interesting design choice, the L2 cache contains sufficient logic to handle semaphore operations without disturbing the main ALU. The latest Itanium processor, however, features a split L2 cache, adding adedicated 1MB L2 cache for instructions and thereby effectively growing the original 256 KB L2 cache, which becomes a dedicated data cache. Most systems sold by enterprise server vendors that contain 4 or more processor sockets use proprietary Non-Uniform Memory Access (NUMA) architectures that supersede the more limited front side bus of 1 and 2 CPU socket servers.
The Itanium 2 bus is occasionally referred to as the Scalability Port, but much more frequently as the McKinley bus. It is a 200 MHz, 128-bit wide, double pumped bus capable of 6.4 GB/s — more than three times the bandwidth of the original Itanium bus, known as the Merced bus. In 2004, Intel released processors with a 266 MHz bus,
increasing bandwidth to 8.5 GB/s. In early 2005, processors with a 10.6 GB/s, 333 MHzbus were released.
Itanium 2 Microprocessor.
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